`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/10/11 23:12:33
// Design Name: 
// Module Name: lab_01_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lab_01_tb(

);
logic            e;//sw[15]
logic            t;//sw[14]
logic   [3:0]    b;//sw[13:10]
logic   [9:0]    a;//sw[9:0]
logic   [15:0]   led;
logic   [6:0]    cn;
logic            dp;
logic   [7:0]    an;
lab_01 LAB(
    .e(e),
    .t(t),
    .b(b),
    .a(a),
    .led(led),
    .cn(cn),
    .dp(dp),
    .an(an)
);
initial begin
    e=1;t=0;
    a=10'b00_0000_0000;
    b=4'b0000;
    repeat(16)begin
        #0.25 b=b+1;
    end
    #0.25 b=4'b1111;
    repeat(20)begin
        #0.25 a=a+1;
    end
    #0.25 t=1;
    #0.25 a=10'b00_0000_0001;
    repeat(10)begin
        #0.25 a=a<<1;
    end
    #0.25 e=0;
    #0.25 a=10'b00_0000_0001;
    repeat(10)begin
        #0.25 a=a<<1;
    end
    repeat(16)begin
        #0.25 b=b+1;
    end
end
endmodule